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The doctoral thesis defended at the Faculty of Informatics, University of Murcia by Ricardo Fernandez Pascual been able to find solutions to the problems caused by transient faults in the interconnection network of a chip.
This research, which was led by professors José Manuel García Eugenio Carrasco and Manuel Acacio, proposes a development from a protocol able to tolerate such failures.
Compared to traditional solutions to solve the problem, based on the redundancy of component, in this thesis proposes a novel development from a coherence protocol can tolerate transient faults with minimal degradation of performance in common case operation.
In this way, we can continue the trend of reducing the size of the transistors that form the microprocessors to build more powerful chips without compromising system reliability.
Due to the technological trends in miniaturization, it is becoming possible to include a greater number of transistors on a single chip and current contain multiple processing cores that communicate with each other through an interconnection network.
The miniaturization of transistors makes them increasingly prone to transient faults because they are affected by impacts of particles from cosmic rays or radioactive impurities from the materials used for packaging.
These faults, for which the thesis offers a remedy, affect the communication between different processing cores included in the chip.
During the development of the thesis, which was awarded the top rating of excellent cum laude with a reference to the European PhD, the author made a stay in the European miconductores company ST Microelectronics. "
Were part of the court, among others, Emre Ozer, Engineer Research and Development "ARM", Cambridge (United Kingdom), Antonio González Colas, director of "Intel UPC Barcelona Research Center, and Professor at the University of Murcia Juan Luis Aragon.
Source: Universidad de Murcia
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