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A doctoral thesis at the University of Murcia mechanisms designed to reduce errors in processor and memory (09/09/2011)

A doctoral dissertation at the Faculty of Informatics, University of Murcia has developed architectural mechanisms that are able to detect and recover faults in processors and memories.

With these designs, author Daniel Sanchez Pedreño, has obtained excellent cum laude, reduces both the hardware cost as the performance penalty of previous proposals, while presenting a new methodology for the study of permanent faults memories as caches.

Low-cost mechanisms to mitigate failures in microarchitectures that collects the thesis focuses on support for scalable parallel applications in shared memory environments, land that remained unexplored to date.

Pedreño Sanchez's research will have an important application of control systems called "critical", which is responsible for managing aircraft, satellites and power stations and have to be doubled or tripled to ensure its smooth operation.

The thesis was supervised by professors from the University of Murcia Juan Luis Aragon and Jose Manuel Garcia Carrasco.

Source: Universidad de Murcia

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